VHDL CODE

In this assignment, you will design andsynthesize the following designs using Xilinx Vivado:

1. 32:1 multiplexer using four 8:1 and one 4:1 multiplexer
2. 5-to-32 decoder
3. A 4-bit wide computational unit according to the following function table:

For eachquestion above, submit vhdl code, RTL schematic, synthesis report, screenshotsof simulation waveforms, and test bench of the designs. Test your design usingat least five test cases. Mark two of the test cases and show the correspondinginputs, expected outputs and simulated outputs for those two cases. The sourcefiles should contain appropriate comments for better understanding.